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Jakub CabalImplementing HDL verification using <a href="https://fosstodon.org/tags/UVM" class="mention hashtag" rel="nofollow noopener" target="_blank">#UVM</a> is annoying and tedious. So <a href="https://fosstodon.org/tags/cocotb" class="mention hashtag" rel="nofollow noopener" target="_blank">#cocotb</a> seems to be the right choice. <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#FPGA</a> <a href="https://fosstodon.org/tags/Python" class="mention hashtag" rel="nofollow noopener" target="_blank">#Python</a> <a href="https://fosstodon.org/tags/systemverilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#systemverilog</a> <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#VHDL</a>

IT NewsDo We Need a New Hardware Description Language? - When you think about hardware description languages, you probably think of Verilog... - <a href="https://hackaday.com/2024/03/15/do-we-need-a-new-hardware-description-language/" rel="nofollow noopener" translate="no" target="_blank">https://hackaday.com/2024/03/15/do-we-need-a-new-hardware-description-language/</a> <a href="https://schleuss.online/tags/systemverilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#systemverilog</a> <a href="https://schleuss.online/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#verilog</a> <a href="https://schleuss.online/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#fpga</a> <a href="https://schleuss.online/tags/hdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#hdl</a>

Clash LanguageTime for my <a href="https://fosstodon.org/tags/introduction" class="mention hashtag" rel="nofollow noopener" target="_blank">#introduction</a> to the Fediverse! :masto_love: Clash is an open source functional hardware description language built on <a href="https://fosstodon.org/tags/Haskell" class="mention hashtag" rel="nofollow noopener" target="_blank">#Haskell</a>. The Clash compiler allows you to use Haskell features like its strong and powerful typesystem as well as use existing Haskell code and libraries in your <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#FPGA</a> and <a href="https://fosstodon.org/tags/ASIC" class="mention hashtag" rel="nofollow noopener" target="_blank">#ASIC</a> designs! You can test your designs right inside the REPL, simulate it alongside other Haskell code or output <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#VHDL</a> / <a href="https://fosstodon.org/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#Verilog</a> / <a href="https://fosstodon.org/tags/SystemVerilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#SystemVerilog</a> code for synthesis.Links in the profile ✨

James against the machineDoes anyone into <a href="https://noise.j-w.au/tags/electronics" class="mention hashtag" rel="nofollow noopener" target="_blank">#electronics</a> and <a href="https://noise.j-w.au/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#fpga</a> have a recommendation for a toolchain and IDE for me, a newcomer to FPGAs?I’ve been told I should “…learn <a href="https://noise.j-w.au/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#Verilog</a>. Or better yet, <a href="https://noise.j-w.au/tags/SystemVerilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#SystemVerilog</a>!”I'm using VSCode, Lushay Code, and <a href="https://noise.j-w.au/tags/OSS" class="mention hashtag" rel="nofollow noopener" target="_blank">#OSS</a>-CAD-Suite. A good path?• MacOS (M2, arm64 CPU) preferred • Windows or NixOS available if there's a compelling reason! • Dev boards: Tang Nano 9K; Tang Nano 20K; iCESugarThank you in advance for any tips/advice/pointers! (Boosts welcome if you know people who know!)

Andrewprobably should have added a few hashtags for better discoverability: <a class="hashtag" href="https://stereophonic.space/tag/systemrdl" rel="nofollow noopener" target="_blank">#SystemRDL</a> <a class="hashtag" href="https://stereophonic.space/tag/systemverilog" rel="nofollow noopener" target="_blank">#SystemVerilog</a> <a class="hashtag" href="https://stereophonic.space/tag/verilog" rel="nofollow noopener" target="_blank">#Verilog</a> <a class="hashtag" href="https://stereophonic.space/tag/c" rel="nofollow noopener" target="_blank">#C</a> <a class="hashtag" href="https://stereophonic.space/tag/fpga" rel="nofollow noopener" target="_blank">#FPGA</a> <a class="hashtag" href="https://stereophonic.space/tag/cpld" rel="nofollow noopener" target="_blank">#CPLD</a> <a class="hashtag" href="https://stereophonic.space/tag/vlsi" rel="nofollow noopener" target="_blank">#VLSI</a> <a class="hashtag" href="https://stereophonic.space/tag/asic" rel="nofollow noopener" target="_blank">#ASIC</a> it is pretty dirty at the moment (see to-do), but I still hope may be useful at least for the niche engineers doing s/w-h/w co-design; also there are no backends for VHDL or Ada yet

YosysHQNot convinced that Formal Verification is worth it? Try our ‘getting started with FV’ package.Including 2 hours of tailored video support to make sure you start getting value fast.* Industrial compliant language support includes <a href="https://fosstodon.org/tags/SystemVerilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#SystemVerilog</a>, <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#VHDL</a> & SVA* Bundled verification IP includes <a href="https://fosstodon.org/tags/RISCV" class="mention hashtag" rel="nofollow noopener" target="_blank">#RISCV</a> and AXI* Access to all our tools including synthesis, <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#FPGA</a>, and mutation coverageJust 1800 euros for 3 months. To get started, book a call with our CSO Matt Venn.<a href="https://lnkd.in/dyD7eez9" rel="nofollow noopener" target="_blank">https://lnkd.in/dyD7eez9</a>

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