Commodore 64 on New FPGA - When it comes to getting retro hardware running again, there are many approaches. ... - https://hackaday.com/2025/07/28/commodore-64-on-new-fpga/ #retrocomputing #commodore64 #tangnano9k #verilog #vic-ii #fpga #hdmi #vhdl

I have not given up on my little #FPGA fantasy console project for the #AnaloguePocket. It’s been a bit dormant because reasons but I just got this little guy to more easily practice and hone my #Verilog skills.

Quartus Prime installed as a flatpak on Fedora

Thanks to @jyhi for his flatpak builder.

The only extra thing you need is to switch off socket=wayland and socket=fallback-x11 so that Quartus is forced to run under XWayland.

https://github.com/jyhi/QuartusPrime-Flatpak/issues

OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at https://digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

I've gone live!

#owncast #streaming #amiga #LiveCoding #RetroGaming #RetroComputing #GameDev #IndieDev #DJ #DJSet #HouseMusic #AnaloguePocket #Verilog #FPGA

https://live.malenfant.net

If you wanna see me struggle with #shaders and #verilog at the same time: I have a stream for you this evening!

https://www.youtube.com/live/HSV3xF_TSqg?si=YmyPzEyXG5p8ryU1

The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl

All the equivalent circuit models of neurons written in an #verilog would be a cool project

Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.

Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog

I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out

#GutenMorgen, Ihr lieben Frühwürmchen!

Eine Gruppe Wissenschaftlys zeigte gestern Abend schon reges Interesse an meinem zweiten Poster, das heute dran ist. Nun überlege ich also, das nochmal etwas umzubauen: die Erklärung "Was ist denn so ein #FPGA überhaupt?" kürzen, dafür dann Blockdiagramm, Datenfluss, #Verilog-Quellcode der beiden wesentlichen Algorithmen drauf.

Hmm …

Habt 1 durchdesignten Tag!

Gifted a new #FPGA dev board this season? PipelineC aims to make #hardware description easier for #embedded folks.
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #HLS
https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup

Is 2025 the year of #FPGA on the desktop?

Please suggest interesting FPGA projects and people to inspire us for the year ahead.

I'm working on a 2D graphics accelerator in #verilog and #riscv assembler.

Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice #HDL #Verilog #VHDL #hardware #embedded

Calling all #HDL hackers! I need help in putting the #MIT #CADR onto a FPGA board. #VHDL, #Verilog, does not matter much. Who is up for a fun challange? #LispMachine

In a better world, #Verilog would have /clk instead of posedge clk, \clk instead of negedge clk, and _clk to mean 'clock is down'.